SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged particular order each Virtual Channel (VC). This implementation is vulnerable HoL blocking, as the switch allocator can allocate only those which available at head VC. this paper, Swapped Buffer (SB) Router architecture proposed schedule input buffers by using SB registers. The VCs designed SBs, allows stored registers along with packet of VC participate SA. concept register minimizes conflicts SA and thus reduces therefore improves NoC. paper proposes priority mechanism prioritize non-head compared case conflict between them. Two methods have been enhance NoC router. First, allocation technique optimize buffer. Next, SB-Router combined Fill further routers. router evaluated experimental results indicate that our design achieves latency improvement 68.75% over (Time-Series) TS-Router for uniform traffic injection rate 0.42 flits/cycle 64 node mesh network moderate power consumption area usage. traces from Princeton Application Repository Shared-Memory Computers (PARSEC) has also evaluated. With achieved reduction latency, method potential serve high-speed operations while mapping different applications on multiple core architectures.